Flash memory controller and method for generating a driving current for flash memories

ABSTRACT

The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims the benefit of priority to Taiwan PatentApplication No. 100142225, filed on Nov. 18, 2011, the entirety of whichis incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to flash memories, and more particularly to flashmemory controllers.

2. Description of the Related Art

A flash memory needs a driving current to drive the operation thereof.Ordinarily, a driving current for a flash memory is provided by a flashmemory controller. The flash memory controller provides a drivingcurrent with a constant level to drive flash memories. Because a singleflash memory stores a limited amount of data, an electronic apparatuswith an increased data capacity comprises more then one flash memorycontrolled by a single flash memory controller.

To increase data capacity of an electronic apparatus, the total numberof flash memories controlled by a flash memory controller is increased.Referring to FIG. 1, a schematic diagram of a flash memory controller102 controlling a plurality of flash memories is shown. The drivingcurrent provided by the flash memory controller 102 must maintain thedata-access operations of eight flash memories 111˜118. Because theflash memory controller 102 merely provides a driving current with aconstant level, and the driving current is shared between the flashmemories 111˜118, each flash memory only obtains a portion of thedriving current. When the total number of the flash memories controlledby the flash memory controller 102 is less than four, the drivingcurrent provided by the flash memory controller 102 can ensurecorrectness of the data-access operations of the flash memories. Whenthe total number of the flash memories controlled by the flash memorycontroller 102 is greater than four, the level of the driving currentobtained by each flash memory cannot maintain correctness of data-accessoperations, and errors are introduced into the data-access operations.

Referring to FIG. 2A, a schematic diagram of a data signal output by aflash memory driven by a driving current with an appropriate level isshown. When the flash memory is driven by a driving current with anappropriate level, the rising time of a data signal output by the flashmemory is 1.2 ns, and the amplitude of the data signal is 3.3V. When theflash memory is driven by a driving current with an insufficient level,the driving current cannot provide enough power to the flash memory, andthe data signal output by the flash memory has a high attenuation and ahigh noise level. Referring to FIG. 2B, a schematic diagram of a datasignal output by a flash memory driven by a driving current with aninsufficient level is shown. When the flash memory is driven by adriving current with an insufficient level, the rising time of a datasignal output by the flash memory is lengthened to 4.45 ns, and theamplitude of the data signal is reduced to 2.8V. Errors are thereforeeasily introduced into the data-access operations of the flash memories.To maintain correctness of the data-access operations of the flashmemory, a driving current with an appropriate level is thereforerequired. A flash memory controller capable of generating a drivingcurrent with an appropriate level is therefore required.

BRIEF SUMMARY OF THE INVENTION

The invention provides a flash memory controller. In one embodiment, theflash memory controller is coupled to a plurality of flash memories, andcomprises a driving current generator and a processor. The drivingcurrent generator generates a driving current to drive the flashmemories. The processor calculates the total number of flash memories,determines a driving current value according to the total number offlash memories, and directs the driving current generator to generatethe driving current with a level greater than or equal to the drivingcurrent value. The driving current value is determined by the processorto be increased with an increase of the total number of flash memories.

The invention also provides a method for generating a driving currentfor flash memories. First, the total number of a plurality of flashmemories coupled to a flash memory controller is calculated. A drivingcurrent value is then determined according to the total number of flashmemories, wherein the driving current value is determined to beincreased with an increase of the total number of flash memories. Adriving current generator is then directed to generate a driving currentwith a level greater than or equal to the driving current value neededto drive the flash memories.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a conventional schematic diagram of a flash memory controllercontrolling a plurality of flash memories;

FIG. 2A is a conventional schematic diagram of a data signal output by aflash memory driven by a driving current with an appropriate level;

FIG. 2B is a conventional schematic diagram of a data signal output by aflash memory driven by a driving current with an insufficient level;

FIG. 3 is a block diagram of an electronic apparatus according to theinvention;

FIG. 4 is a flowchart of a method for determining a level of drivingcurrent according to the total number of flash memories according to theinvention;

FIG. 5 is a schematic diagram of an embodiment of a driving currenttable according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

Referring to FIG. 3, a block diagram of an electronic apparatus 300according to the invention is shown. In one embodiment, the electronicapparatus 300 comprises a flash memory controller 302 and N flashmemories 331˜33N. The flash memory controller 302 comprises a pluralityof chip enable pins CE₁, CE₂, CF₃, . . . , CE_(N) respectively coupledto the flash memories 331, 332, 333, . . . , 33N. In one embodiment, theflash memory controller 302 comprises a processor 312 and a drivingcurrent generator 314. A plurality of command lines CMD₁, CMD₂, CMD₃, .. . , CMD_(N) are respectively coupled between the processor 312 and theflash memories 331, 332, 333, . . . , 33N. The processor 312 transmitsdata access commands to the flash memories 331˜33N via the command linesCMD₁˜CMD_(N). When the flash memories 331˜33N receive data accesscommands, the flash memories 331˜33N send response information back tothe processor 312 via the command lines CMD₁˜CMD_(N).

The driving current generator 314 generates a driving current. Thedriving current drives the flash memories 331, 332, 333, . . . , 33N viathe chip enable pins CE₁, CE₂, CE₃, . . . , CE_(N). In one embodiment,the flash memory controller 302 comprises a driving current valueregister 318. The driving current value register 318 stores a drivingcurrent value. When the driving current value register 318 stores adriving current value, the driving current generator 314 generates adriving current with a level greater than or equal to the drivingcurrent value. The processor 312 therefore can amend the driving currentvalue stored in the driving current value register to change the levelof the driving current generated by the driving current generator 314.

The processor 312 calculates a total number N of flash memories 331˜33Ncoupled to the flash memory controller 302, and sets the driving currentvalue stored in the driving current value register 318 according to thetotal number N of flash memories 331˜33N. The driving current generator314 therefore generates a driving current with an appropriate levelcorresponding to the total number of flash memories 331˜33N. In oneembodiment, the driving current value increases with an increase of thetotal number N of flash memories 331˜33N. Each of the flash memories331˜33N therefore is allotted a portion of the driving current with alevel which is enough to drive the operations thereof. In oneembodiment, the processor 312 determines the driving current valuecorresponding to the total number N of the flash memories 331˜33Naccording to an algorithm, wherein the algorithm indicates a mappingrelationship between the total number N of the flash memories and thelevel of driving current.

In another embodiment, the flash memory controller 302 comprises arandom access memory (RAM) 316. The RAM 316 stores a driving currenttable 320, and a plurality of total numbers of flash memories andcorresponding predetermined driving current values are stored in thedriving current table 320. When the processor 312 calculates the totalnumber N of flash memories 331˜33N, the processor 312 searches thedriving current table 320 for the predetermined driving current valuecorresponding to the total number N of flash memories 331˜33N as thedriving current value.

Referring to FIG. 5, a schematic diagram of an embodiment of a drivingcurrent table 320 according to the invention is shown. For example, whenthe total number of flash memories controlled by the flash memorycontroller 302 is 1, the predetermined driving current value is 4 mA.When the total number of flash memories controlled by the flash memorycontroller 302 is 4, the predetermined driving current value is 8 mA.When the total number of flash memories controlled by the flash memorycontroller 302 is 64, the predetermined driving current value is 64 mA.Thus, when the total number of flash memories is increased, thepredetermined driving current value is also increased to generate adriving current with a level corresponding to the total number of flashmemories.

Referring to FIG. 4, a flowchart of a method 400 for determining thelevel of driving current according to a total number of flash memoriesaccording to the invention is shown. First, power to the electronicapparatus 300 is switched on. The flash memory controller 302 thendetermines whether a plurality of chip enable pins CE₁˜CE_(N) of theflash memory controller 302 are coupled to a plurality of flash memories331˜33N (step 402). In one embodiment, the processor 312 determineswhether the chip enable pins CE₁˜CE_(N) are coupled to the flashmemories 331˜33N according to the voltages on the chip enable pinsCE₁˜CE_(N), and then determines the total number of flash memories331˜33N according to the voltages on the chip enable pins CE₁˜CE_(N).

The processor 312 then sends a specific command to the flash memories331˜33N (step 404). After the flash memories 331˜33N receive thespecific command, each of the flash memories 331˜33N sends responseinformation back to the processor 312, and the processor 312 determinesthe total number N of flash memories 331˜33N according to the responseinformation sent from the flash memories 331˜33N (step 406). In oneembodiment, the specific command is a read flash identifier commandwhich requests the flash memories 331˜33N to read the identifiersthereof. The processor 312 can then determine the total number of flashmemories 331˜33N according to the total number of flash identifiersreceived by the flash memory controller 302. In another embodiment, thespecific command is a read command or a write command. When the flashmemories 331˜33N send read response information or write responseinformation to the flash memory controller 302, the processor 312determines the total number of flash memories 331˜33N according to theread response information or write response information received by theflash memory controller 302.

After the processor 312 determines the total number of flash memories331˜33N, the processor 312 searches the driving current table 320 for apredetermined driving current value corresponding to the total number offlash memories 331˜33N as the driving current value (step 408). Theprocessor 312 then writes the driving current value to the drivingcurrent value register 318 (step 410). The driving current generator 314then generates a driving current with a level greater than or equal tothe driving current value stored in the driving current value register318 to drive the flash memories 331˜33N (step 412). Because the level ofthe driving current is determined according to the total number N offlash memories 331˜33N, the driving current has enough power to driveall of the flash memories 331˜33N controlled by the flash memorycontroller 302. Signal attenuation and noise increase due to a drivingcurrent with an insufficient level is therefore avoided, and data-accesserrors are therefore also avoided.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

What is claimed is:
 1. A flash memory controller, coupled to a pluralityof flash memories, comprising: a driving current generator, generating adriving current to drive the flash memories; and a processor,calculating a total number of the flash memories, determining a drivingcurrent value according to the total number of the flash memories, anddirecting the driving current generator to generate the driving currentwith a level greater than or equal to the driving current value; whereinthe driving current value is determined by the processor to be increasedwith an increase of the total number of flash memories, wherein theflash memory controller is coupled to the flash memories via a pluralityof chip enable pins, and the processor determines the total number ofthe flash memories according to the voltages of the chip enable pins. 2.The flash memory controller as claimed in claim 1, wherein the flashmemory controller sends a specific command to the flash memories,receives response information corresponding to the specific command fromthe flash memories, and determines the total number of the flashmemories according to the response information.
 3. The flash memorycontroller as claimed in claim 2, wherein the specific command requeststhe flash memories to read identifiers of the flash memories, and theresponse information comprises the identifiers sent from the flashmemories to the flash memory controller.
 4. The flash memory controlleras claimed in claim 2, wherein the specific command requests the flashmemories to access data from the flash memories, and the responseinformation comprises the execution status of data-access operationsperformed by the flash memories.
 5. The flash memory controller asclaimed in claim 1, wherein the flash memory controller furthercomprises a driving current value register, the processor writes thedriving current value to the driving current value register, and thedriving current generator generates the driving current according to thedriving current value stored in the driving current value register. 6.The flash memory controller as claimed in claim 1, wherein the processordetermines the driving current value according to an algorithm, and thealgorithm indicates a mapping relationship between the driving currentvalue and the total number of the flash memories.
 7. The flash memorycontroller as claimed in claim 1, wherein the flash memory controllercomprises a random access memory, a driving current table is stored inthe random access memory, a plurality of predetermined driving currentvalues and a plurality of corresponding total numbers of the flashmemories are recorded in the driving current table, and the processorsearches the driving current table for the predetermined driving currentvalue corresponding to the total number of the flash memories as thedriving current value.
 8. A method for generating a driving current forflash memories, comprising: calculating the total number of a pluralityof flash memories coupled to a flash memory controller; determining adriving current value according to the total number of the flashmemories; and directing a driving current generator to generate adriving current with a level greater than or equal to the drivingcurrent value to drive the flash memories; wherein the driving currentvalue is determined to be increased with an increase of the total numberof the flash memories, wherein the flash memory controller is coupled tothe flash memories via a plurality of chip enable pins, anddetermination of the driving current value comprises determining thetotal number of the flash memories according to the voltages of the chipenable pins.
 9. The method as claimed in claim 8, wherein determinationof the driving current value comprises: sending a specific command bythe flash memory controller to the flash memories; receiving responseinformation corresponding to the specific command by the flash memorycontroller from the flash memories; and determining the total number ofthe flash memories according to the response information.
 10. The methodas claimed in claim 9, wherein the specific command requests the flashmemories to read the identifiers of the flash memories, and the responseinformation comprises the identifiers sent from the flash memories tothe flash memory controller.
 11. The method as claimed in claim 9,wherein the specific command requests the flash memories to access datafrom the flash memories, and the response information comprises theexecution status of data-access operations performed by the flashmemories.
 12. The method as claimed in claim 8, wherein direction of thedriving current generator comprises: writing the driving current valueto a driving current value register of the flash memory controller; anddirecting the driving current generator to generate the driving currentaccording to the driving current value stored in the driving currentvalue register.
 13. The method as claimed in claim 8, whereindetermination of the driving current value comprises determining thedriving current value according to an algorithm, wherein the algorithmindicates a mapping relationship between the driving current value andthe total number of the flash memories.
 14. The method as claimed inclaim 8, wherein determination of the driving current value comprises:storing a driving current table in a random access memory of the flashmemory controller, wherein a plurality of predetermined driving currentvalues and a plurality of corresponding total numbers of the flashmemories are recorded in the driving current table; and searching thedriving current table for the predetermined driving current valuecorresponding to the total number of the flash memories as the drivingcurrent value.